Concurrent error detection in bit-serial normal basis multiplication over GF(2m) using multiple parity prediction scheme's

Authors:
Chiou-Yng Lee;Pramod Kumar Meher;Jagdish Chandra Patra
Affiliations:
Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, Taoyuan, Taiwan;Department of Communication Systems, Institute for Infocomm Research, Singapore;School of Computer Engineering. Nanyang Technological University, Singapore
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.