On concurrent detection of errors in polynomial basis multiplication

Authors:
Siavash Bayat-Sarmadi;M. Anwar Hasan
Affiliations:
Department of Electrical and Computer Engineering and the Center for Applied Cryptographic Research, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering and the Center for Applied Cryptographic Research, University of Waterloo, Waterloo, ON, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

The detection of errors in arithmetic operations is an important issue. This paper discusses the detection of multiple-bit errors due to faults in bit-serial and bit-parallel polynomial basis (PB) multipliers over binary extension fields. Our approach is based on multiple parity bits. Experimental results presented here show that due to an increase in the number of parity bits, the area overhead tends to increase linearly, but the probability of error detection approaches unity fairly quickly, e.g., for eight parity bits. In bit-serial implementation of a GF(2163) PB multiplier using eight parity bits, the area overhead and the probability of error detection are 10.29% and 0.996, respectively. This is achieved without any increase in the computation time of the GF(2163) PB multiplier.