Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Introduction to finite fields and their applications
Introduction to finite fields and their applications
Error-control coding for computer systems
Error-control coding for computer systems
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault-tolerant computer system design
Fault-tolerant computer system design
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
IEEE Transactions on Computers
Error-Control Coding for Data Networks
Error-Control Coding for Data Networks
An Introduction to Error Correcting Codes with Applications
An Introduction to Error Correcting Codes with Applications
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Error Control Coding, Second Edition
Error Control Coding, Second Edition
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
IEEE Transactions on Computers
Montgomery Residue Representation Fault-Tolerant Computation in GF(2k)
ACISP '08 Proceedings of the 13th Australasian conference on Information Security and Privacy
Fault-tolerant finite field computation in the public key cryptosystems
AAECC'07 Proceedings of the 17th international conference on Applied algebra, algebraic algorithms and error-correcting codes
Design and implementation of robust embedded processor for cryptographic applications
Proceedings of the 3rd international conference on Security of information and networks
Robust finite field arithmetic for fault-tolerant public-key cryptography
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
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Cryptographic schemes, such as authentication, confidentiality, and integrity, rely on computations in very large finite fields, whose hardware realization may require millions of logic gates. In a straightforward design, even a single fault in such a complex circuit is likely to yield an incorrect result and may be exploited by an attacker to break the cryptosystem. In this regard, we consider computing over finite fields in presence of certain faults in multiplier circuits. Our work reported here deals with errors caused by such faults in polynomial basis multipliers over finite fields of characteristic two and presents a scheme to correct single errors. Towards this, pertinent theoretical results are derived, and both bit-parallel and bit-serial fault tolerant multipliers are proposed.