Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
IEEE Transactions on Computers
Towards fault-tolerant cryptographic computations over finite fields
ACM Transactions on Embedded Computing Systems (TECS)
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
Journal of Electronic Testing: Theory and Applications
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
IEEE Transactions on Computers
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent error detection in Reed-Solomon encoders and decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of robust embedded processor for cryptographic applications
Proceedings of the 3rd international conference on Security of information and networks
Robust finite field arithmetic for fault-tolerant public-key cryptography
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
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In many of cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation may require millions of logic gates. It is a complex and costly task to develop such large finite field multipliers which will always yield error free outputs. In this effect, this paper considers fault tolerant multiplication in finite fields. It deals with detection of errors of bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. Our approach is to partition the multiplier structure into a number of smaller computational units and use the parity prediction technique to detect errors.