Architectures for exponentiation in GF (2n)
Proceedings on Advances in cryptology---CRYPTO '86
IEEE Transactions on Computers
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Discrete Applied Mathematics
IEEE Transactions on Computers - Special issue on computer arithmetic
Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application
IEEE Transactions on Computers
Signed Digit Representations of Minimal Hamming Weight
IEEE Transactions on Computers
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
IEEE Transactions on Computers
Architecture For A Low Complexity Rate-Adaptive Reed-Solomon Encoder
IEEE Transactions on Computers
Closed-Form Expression for the Average Weight of Signed-Digit Representations
IEEE Transactions on Computers
Optimal Left-to-Right Binary Signed-Digit Recoding
IEEE Transactions on Computers - Special issue on computer arithmetic
Efficient exponentiation using weakly dual basis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A New Construction of Massey-Omura Parallel Multiplier over GF(2^{m})
IEEE Transactions on Computers
New Minimal Modified Radix-r Representation with Applications to Smart Cards
PKC '02 Proceedings of the 5th International Workshop on Practice and Theory in Public Key Cryptosystems: Public Key Cryptography
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
IEEE Transactions on Computers
An efficient technique for synthesis and optimization of polynomials in GF(2m)
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
C-testable bit parallel multipliers over GF(2m)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A loopless gray code for minimal signed-binary representations
ESA'05 Proceedings of the 13th annual European conference on Algorithms
WISA'04 Proceedings of the 5th international conference on Information Security Applications
Integration, the VLSI Journal
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In this paper, exponentiation of a primitive root in GF(2m) is considered. Signed digit (SD) number representation is used to efficiently represent the exponent and the corresponding algorithms and structures for exponentiation are developed. For primitive multiplications required in exponentiations, extended bidirectional linear feedback shift registers are proposed and used for the cases where the exponent is represented as a binary or a radix-4 SD number. Comparisons are made with other methods on the bases of space, time, and possible power consumption. Since the proposed structures can effectively reduce power and area when implemented in VLSI, they are especially suitable for battery powered portable devices.