VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Architectures for exponentiation in GF (2n)
Proceedings on Advances in cryptology---CRYPTO '86
Lecture Notes in Computer Science on Advances in Cryptology-EUROCRYPT'88
IEEE Transactions on Computers
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Efficient exponentiation using weakly dual basis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Architectures for Arithmetic over GF(2^m)
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Communication-Computation Trade-off in Executing ECDSA in a Contactless Smartcard
Designs, Codes and Cryptography
Hi-index | 14.98 |
Two exponentiation circuits are proposed. Using the fact that squaring is a linear operation over GF(2/sup n/), a time-space tradeoff in smartcard-based circuitry is presented. It is shown how multiplication is performed by a single shift, based on replacing the public key alpha /sup a/ in GF(2/sup n/) by its minimal polynomial. Other considerations, related to structure regularity and the possible use of dynamic shift registers, are also treated.