VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Spread Spectrum Systems
Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
Efficient Multiplier Architectures for Galois Fields GF(24n)
IEEE Transactions on Computers
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
Architectures for Exponentiation Over GD(2/sup n/) Adopted for Smartcard Application
IEEE Transactions on Computers
Bit-Level Systolic Array for Fast Exponentiation in GF(2/sup m/)
IEEE Transactions on Computers
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
Journal of Electronic Testing: Theory and Applications
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
Low-complexity bit-parallel systolic multipliers over GF(2m)
Integration, the VLSI Journal
Multiplexer-based bit-parallel systolic multipliers over GF(2m)
Computers and Electrical Engineering
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
Fast arithmetic architectures for public-key algorithms over Galois fields GF((2n)m)
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
Efficient semisystolic architectures for finite-field arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme.