Multiplexer-based bit-parallel systolic multipliers over GF(2m)

Authors:
Chiou-Yng Lee
Affiliations:
Department of Computer Information and Network Engineering, Lunghwa University of Science and Technology, No. 300, Sec. 1, Wanshou Road, Taoyuan County 333, Taiwan, ROC
Venue:
Computers and Electrical Engineering
Year:
2008

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Abstract

Two novel systolic architectures are presented in this paper for polynomial basis finite field multipliers. Using cut-set systolization technique and modified Booth's recording, we have derived here an efficient realization of multiplexer-based bit-parallel systolic multipliers over GF(2^m). Our multipliers save about 19% space complexity as compared to traditional multipliers, and involve nearly half of the time-complexity of the corresponding existing design. It is shown that the proposed systolic architectures have significantly lower time-area product than existing systolic multipliers. For cryptographic applications, our proposed architectures can have better the time and space complexity. Moreover, these new multipliers are highly regular, modular, and therefore, well-suited for VLSI implementation.