Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Algorithms for Iterative Array Multiplication
IEEE Transactions on Computers
A Single Chip Parallel Multiplier by MOS Technology
IEEE Transactions on Computers
Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators
Journal of VLSI Signal Processing Systems
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
A new array architecture for signed multiplication using Gray encoded radix-2m operands
Integration, the VLSI Journal
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
A high-speed radix-4 multiplexer-based array multiplier
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Multiplexer-based bit-parallel systolic multipliers over GF(2m)
Computers and Electrical Engineering
Low-complexity bit-parallel multiplier over GF(2m) using dual basis representation
Journal of Computer Science and Technology
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
Journal of Signal Processing Systems
Low-complexity bit-parallel multipliers for a class of GF(2m) based on modified Booth's algorithm
International Journal of Computers and Applications
High speed multiplier based on the algorithm of Chinese abacus
ACACOS'10 Proceedings of the 9th WSEAS international conference on Applied computer and applied computational science
The new architecture of Chinese abacus multiplier
WSEAS Transactions on Computers
Low power and high speed multiplier design with row bypassing and parallel architecture
Microelectronics Journal
A low error and high performance multiplexer-based truncated multiplier
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information Processing Letters
Information Processing Letters
| Hi-index | 14.98 |
A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization