Multiplexer-Based Array Multipliers
IEEE Transactions on Computers
The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
The new architecture of radix-4 Chinese abacus adder
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
A 40-ns 17-Bit by 17-Bit Array Multiplier
IEEE Transactions on Computers
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
On complexity of normal basis multiplier using modified Booth's algorithm
AIC'07 Proceedings of the 7th Conference on 7th WSEAS International Conference on Applied Informatics and Communications - Volume 7
Trade-offs in multiplier block algorithms for low power digit-serial FIR filters
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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This study demonstrated a 4×4 bits multiplier that was based on the Chinese abacus. Comparing the simulation results of this work with the speed and power consumption of the 4×4 bits Braun array multiplier, this 4×4 bits abacus multiplier showed a 19.7% and 10.6% delay improvement in 0.35µm and 0.18µm technology respectively than that of the 4×4 bits Braun array multiplier, while power consumption of the 4×4 bits abacus multiplier was 8.7% and 18% lower respectively.The performance: power-consumption*delay of the abacus multiplier is respectively, less about 23.2% and 23.5% also.