Trade-offs in multiplier block algorithms for low power digit-serial FIR filters

Authors:
Kenny Johansson;Oscar Gustafsson;Lars Wanhammar
Affiliations:
Department of Electrical Engineering, Linköping University, Linköping, Sweden;Department of Electrical Engineering, Linköping University, Linköping, Sweden;Department of Electrical Engineering, Linköping University, Linköping, Sweden
Venue:
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Year:
2006

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Abstract

In this paper trade-offs in digit-serial multiplier blocks are studied. Three different algorithms for realization of multiplier blocks are compared in terms of complexity and adder depth. Among the three algorithms is a new algorithm that reduces the number of shifts while the number of adders is on average the same. Hence, the total complexity is reduced for multiplier blocks implemented using digit-serial arithmetic, where shift operations have a hardware cost. An example implementation is used to compare the power consumption for five approaches: the three algorithms, using separate multipliers based on CSD representation, and an algorithm based on subexpression sharing. The design of low power multiplier blocks is shown to be a more complicated problem than to reduce the complexity. A main factor that needs to be considered is adder depth. Furthermore, digit-serial shifts will reduce glitch propagation.