Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
Journal of VLSI Signal Processing Systems
FIR filter synthesis algorithms for minimizing the delay and the number of adders
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An improved synthesis method for low power hardwired FIR filters
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Some Optimizations of Hardware Multiplication by Constant Matrices
IEEE Transactions on Computers
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An interactive codesign environment for domain-specific coprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 43rd annual Design Automation Conference
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Optimization of area in digital FIR filters using gate-level metrics
Proceedings of the 44th annual Design Automation Conference
Multiplierless implementation of rotators and FFTs
EURASIP Journal on Applied Signal Processing
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
An approximate algorithm for the multiple constant multiplications problem
Proceedings of the 21st annual symposium on Integrated circuits and system design
Area optimization algorithms in high-speed digital FIR filter synthesis
Proceedings of the 21st annual symposium on Integrated circuits and system design
Complexity Reduction of Constant Matrix Computations over the Binary Field
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Signal Processing
Journal of Signal Processing Systems
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New reconfigurable architectures for implementing FIR filters with low complexity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
Parallel implementation of convolution encoder for software defined radio on DSP architecture
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Exploration of heterogeneous FPGAs for mapping linear projection designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel FIR filter implementation using truncated MCM technique
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Techniques for avoiding sign-extension in multiple constant multiplication
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Design of multiplierless FIR filters with an adder depth versus filter order trade-off
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
Trade-offs in multiplier block algorithms for low power digit-serial FIR filters
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Finding the optimal tradeoff between area and delay in multiple constant multiplications
Microprocessors & Microsystems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficient solution of this problem can yield significant improvements in important design parameters like implementation area or power consumption. In this paper, a new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented. The performance of our method is demonstrated primarily on a finite-duration impulse response filter design. The idea is to implement a set of constant multiplications as a set of add-shift operations and to optimize these with respect to the common subexpressions afterwards. We show that the number of add/subtract operations can be reduced significantly this way. The applicability of the presented algorithm to the different high-level synthesis tasks is also indicated. Benchmarks demonstrating the algorithm's efficiency are included as well