Incremental tree height reduction for high level synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Effective partial redundancy elimination
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Synthesis of multiplier-less FIR filters with minimum number of additions
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Software—Practice & Experience
The disjunctive decomposition of logic functions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
Advanced compiler design and implementation
Advanced compiler design and implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using symbolic algebra in algorithmic level DSP synthesis
Proceedings of the 38th annual Design Automation Conference
ACM Transactions on Programming Languages and Systems (TOPLAS)
Digital Signal Processing: A Computer-Based Approach
Digital Signal Processing: A Computer-Based Approach
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Low Power Embedded Software Optimization Using Symbolic Algebra
Proceedings of the conference on Design, automation and test in Europe
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Energy Efficient Hardware Synthesis of Polynomial Expressions
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Factoring and eliminating common subexpressions in polynomial expressions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Complexity reduction of digital filters using shift inclusive differential coefficients
IEEE Transactions on Signal Processing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A graph theoretic approach for synthesizing very low-complexity high-speed digital filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A process variation aware low power synthesis methodology for fixed-point FIR filters
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variation-aware low-power synthesis methodology for fixed-point FIR filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Constant multiplications can be efficiently implemented in hardware by converting them into a sequence of nested additions and shift operations. They can be optimized further by finding common subexpressions among these operations. In this work, we present algebraic methods for eliminating common subexpressions. Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic. In this work we use the concepts of two of these methods, namely rectangle covering and fast extract (FX) and adapt them to the problem of optimizing linear arithmetic expressions. The main advantage of using such methods is that we can optimize systems consisting of multiple variables, which is not possible using the conventional optimization techniques. Our optimizations are aimed at reducing the area and power consumption of the hardware, and experimental results show up to 30.3% improvement in the number of operations over conventional techniques. Synthesis and simulation results show up to 30% area reduction and up to 27% power reduction. We also modified our algorithm to perform delay aware optimization, where we perform common subexpression elimination such that the delay is not exceeded beyond a particular value.