DAC '94 Proceedings of the 31st annual Design Automation Conference
Techniques for low power realization for FIR filters
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Optimized code generation of multiplication-free linear transforms
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimization method for broadband modem FIR filter design using common subexpression elimination
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
An improved synthesis method for low power hardwired FIR filters
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
Hi-index | 0.00 |
Abstract: In this paper we present optimizing transformations to minimize the number of additions+subtractions in both the direct form (/spl Sigma/ A/sub i/X/sub n-i/ based) and its transposed form (Multiple Constant Multiplication based) implementation of FIR filters. These transformations are based on the iterative elimination of 2-bit common subexpressions in the coefficients binary representations. We give detailed description of the algorithms and present results for eight low pass FIR filters with the number of coefficients ranging from 16 to 128. The results show upto 35% reduction in the number of additions+subtractions to implement /spl Sigma/ A/sub i/X/sub n-i/ based FIR filter structures and upto 38% reduction to implement MCM based structures.