Discrete-time signal processing
Discrete-time signal processing
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesis of multiplier-less FIR filters with minimum number of additions
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA-based tool path computation: an application for shoe last machining on CNC lathes
Computers in Industry
FPGA-based tool path computation
Computers in Industry
New approach to look-up-table design and memory-based realization of FIR digital filter
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Generic systolic array for run-time scalable cores
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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In this paper we present coefficient memory vs number of additions tradeoff in distributed arithmetic based implementation of FIR filters. Such a capability is key to be able to explore a wider search space during system level design. We present two techniques based on multiple memory banks and multirate architectures to achieve this tradeoff. These techniques along with 1-bit-at-a-time and 2-bits-at-a-time data access mechanisms enable as many as 16 different data points in the area-delay space. We present analytical expressions to compute coefficient memory size and number of additions for these implementations. We present results for all the 16 DA based implementations of three FIR filters with two values of input data precision. We also present the resultant area-delay curves for these filters.