IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Effective Lower Bounding Techniques for Pseudo-Boolean Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 43rd annual Design Automation Conference
Optimization of area in digital FIR filters using gate-level metrics
Proceedings of the 44th annual Design Automation Conference
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Resource sharing among mutually exclusive sum-of-product blocks for area reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An approximate algorithm for the multiple constant multiplications problem
Proceedings of the 21st annual symposium on Integrated circuits and system design
Area optimization algorithms in high-speed digital FIR filter synthesis
Proceedings of the 21st annual symposium on Integrated circuits and system design
Complexity Reduction of Constant Matrix Computations over the Binary Field
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Area-reducing sharing of mutually exclusive multiplier, MAC, adder and subtractor blocks
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple constant multiplication through residue number system
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Finding the optimal tradeoff between area and delay in multiple constant multiplications
Microprocessors & Microsystems
Efficient arithmetic sum-of-product (SOP) based multiple constant multiplication (MCM) for FFT
Proceedings of the International Conference on Computer-Aided Design
Integration, the VLSI Journal
Design of digit-serial FIR filters: algorithms, architectures, and a CAD tool
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose an exact algorithm that maximizes the sharing of partial terms in multiple constant multiplication (MCM) operations. We model this problem as a Boolean network that covers all possible partial terms which may be used to generate the set of coefficients in the MCM instance. The PIs to this network are shifted versions of the MCM input. An AND gate represents an adder or a subtracter, i.e., an AND gate generates a new partial term. All partial terms that have the same numerical value are ORed together. There is a single output which is an /spl and/ over all the coefficients in the MCM. We cast this problem into a 0-1 integer linear programming (ILP) problem by requiring that the output is asserted while minimizing the total number of AND gates that evaluate to one. A SAT-based solver is used to obtain the exact solution. We argue that for many real problems the size of the problem is within the capabilities of current SAT solvers. We present results using binary, CSD and MSD representations. Two main conclusions can be drawn from the results. One is that, in many cases, existing heuristics perform well, computing the best solution, or one close to it. The other is that the flexibility of the MSD representation does not have a significant impact in the solution obtained.