DAC '94 Proceedings of the 31st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Optimization of area in digital FIR filters using gate-level metrics
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Over the years many efficient algorithms for the multiplierless design of multiple constant multiplications (MCMs) have been introduced. These algorithms primarily focus on finding the fewest number of addition/subtraction operations that generate the MCM. Although the complexity of an MCM design is decreased by reducing the number of operations, their solutions may not lead to an MCM design with optimal area at gate-level since they do not consider the implementation costs of the operations in hardware. This article introduces two approximate algorithms that aim to optimize the area of the MCM operation by taking into account the gate-level implementation of each addition and subtraction operation which realizes a constant multiplication. To find the optimal tradeoff between area and delay, the proposed algorithms are further extended to find an MCM design with optimal area under a delay constraint. Experimental results clearly indicate that the solutions of the proposed algorithms lead to significantly better MCM designs at gate-level when compared to those obtained by the solutions of algorithms designed for the optimization of the number of operations.