IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital filter synthesis based on minimal signed digit representation
Proceedings of the 38th annual Design Automation Conference
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Search algorithms for the multiple constant multiplications problem: Exact and approximate
Microprocessors & Microsystems
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Efficient shift-adds design of digit-serial multiple constant multiplications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The last two decades have seen tremendous effort on the development of high-level synthesis algorithms for efficient realization of the multiplication of a variable by a set of constants using only addition, subtraction, and shift operations. These algorithms generally target the minimization of the number of adders and subtractors, assuming that shifts are realized using only wires due to the bit-parallel processing of the input data. On the other hand, digit-serial architectures offer alternative low-complexity designs since digit-serial operators occupy less area and are independent of the data wordlength. However, in this case, shifts are no longer free in terms of hardware and require D flip-flops. Moreover, each digit-serial addition, subtraction, and shift operation has different implementation cost at gate-level. Hence, this article introduces high-level algorithms that optimize the area of digit-serial constant multiplications under the shift-adds architecture by taking into account the implementation cost of each operation at gate-level. Experimental results indicate that our high-level algorithms obtain better solutions than prominent algorithms designed for the minimization of the number of operations in terms of gate-level area and their solutions lead to less complex digit-serial MCM designs. It is also shown that the use of shift-adds architecture yields significant area reductions when compared to the constant multiplications designed using generic digit-serial constant multipliers.