Layout-driven architecture synthesis for high-speed digital filters
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Two-stage ensemble memetic algorithm: Function optimization and digital IIR filter design
Information Sciences: an International Journal
Fixed-point digital IIR filter design using two-stage ensemble evolutionary algorithm
Applied Soft Computing
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We present a graph theoretical methodology that reduces the implementation complexity of the multiplication of a constant vector and a scalar. The complexity of implementation is defined as the required amount of computations like additions. The proposed approach is called minimally redundant parallel (MRP) optimization and is mainly presented in a finite impulse response (FIR) filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients (SIDCs) together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The problem is formulated using a graph in which vertices and edges represent coefficients and computational cost (number of resources). The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented. The proposed approach is compared with common-subexpression elimination to show slightly better results and is combined with it for further reduction of complexity. Simulation results show that 50-60% complexity reduction is achieved by only applying the MRP algorithm, and 70% complexity reduction is obtainable by combining it with common-subexpression elimination under a delay constraint of two or three.