Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computers and Electrical Engineering
Algebraic Methods for Optimizing Constant Multiplications in Linear Systems
Journal of VLSI Signal Processing Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Long-Point FFT Processing Based on Twiddle Factor Table Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
High-level synthesis algorithm for the design of reconfigurable constant multiplier
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Time-efficient single constant multiplication based on overlapping digit patterns
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A canonic-signed-digit coded genetic algorithm for designing finite impulse response digital filter
Digital Signal Processing
A novel optimal single constant multiplication algorithm
Proceedings of the 47th Design Automation Conference
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Journal of Signal Processing Systems
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In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters based on the MSD representation. The hardware complexity of a digital signal processing system is dependent on the number system used for the implementation. Although the canonical signed digit (CSD) representation is widely employed, as it is unique and guarantees the minimal number of nonzero digits for a constant, the MSD representation provides multiple representations that have the same number of nonzero digits as the CSD representation. The proposed filter synthesis algorithm utilizes this redundancy of the MSD representation to make common subexpressions, as many as possible, leading to smaller filters. By applying the proposed algorithm to the hardware synthesis of finite impulse response filters, the authors obtained multiplier blocks that are 7% smaller than those generated from the CSD representation.