Parallel reduced area multipliers
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
Variations on Truncated Multiplication
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Multiplierless multiple constant multiplication
ACM Transactions on Algorithms (TALG)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multiplication is performed frequently when implementing finite impulse response (FIR) filters. In most cases, rounded products are necessary to circumvent the growth of word length in order to reduce the area requirement and power dissipation and to speed up the circuit. However, due to rounding or truncating, errors are caused. In addition, in the FIR filter implementation, because of internal truncation, the coefficient multiplication varies based on the input. This makes directly analyzing its frequency response impossible. In this paper, FIR filter implementation using truncated multiple constant multiplication (MCM) is proposed, while developing a method to estimate the error due to truncation. Simulation indicates that our technique can reduce the number of full adders by nearly 30 percent, compared to traditional MCM algorithms, while only causing small errors in the frequency response.