Demand driven simulation: BACKSIM
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automatic generation of compiled simulations through program specialization
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Advanced compiler design and implementation
Advanced compiler design and implementation
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Readings in Hardware/Software Co-Design
Readings in Hardware/Software Co-Design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Sophomore Course in Codesign
Computer
Computer
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Interactive Cosimulation with Partial Evaluation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Proceedings of the 42nd annual Design Automation Conference
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design with race-free hardware semantics
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An information-theoretic model for adaptive side-channel attacks
Proceedings of the 14th ACM conference on Computer and communications security
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Formally Bounding the Side-Channel Leakage in Unknown-Message Attacks
ESORICS '08 Proceedings of the 13th European Symposium on Research in Computer Security: Computer Security
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Semantics and verification of a language for modelling hardware architectures
Formal methods and hybrid real-time systems
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Automatically deriving information-theoretic bounds for adaptive side-channel attacks
Journal of Computer Security
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Energy-efficient embedded systems rely on domain-specific coprocessors for dedicated tasks such as baseband processing, video coding, or encryption. We present a language and design environment called GEZEL that can be used for the design, verification and implementation of such coprocessor-based systems.The GEZEL environment creates a platform simulator by combining a hardware simulation kernel with one or more instruction-set simulators. The hardware part of the platform is programmed in GEZEL, a deterministic, cycle-true and implementation-oriented hardware description language. GEZEL designs are scripted, allowing the hardware configuration of the platform simulator to be changed quickly without going through lengthy recompiles. For this reason, we call the environment interactive. We present the execution ladder as an optimization framework to balance interactivity against simulation speed.We demonstrate our approach using several designs including an AES encryption coprocessor and a Viterbi decoding coprocessor. We discuss the advantages of our approach as opposed to more conventional approaches using SystemC and Verilog/VHDL.