Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
A Family of Jacobians Suitable for Discrete Log Cryptosystems
CRYPTO '88 Proceedings of the 8th Annual International Cryptology Conference on Advances in Cryptology
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A High Performance Reconfigurable Elliptic Curve Processor for GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Reconfigurable Elliptic Curve Cryptosystems on a Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An interactive codesign environment for domain-specific coprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
IEEE Transactions on Computers
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
A resource optimized Processor Core for FPGA based SoCs
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
On parallelization of high-speed processors for elliptic curve cryptography
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Superscalar coprocessor for high-speed curve-based cryptography
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware/software co-design of elliptic curve cryptography on an 8051 microcontroller
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 µP
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Complexity analysis of finite field digit serial multipliers on FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
GF(2m) finite-field multipliers with reduced activity variations
WAIFI'12 Proceedings of the 4th international conference on Arithmetic of Finite Fields
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Most hardware/software (HW/SW) codesigns of Elliptic Curve Cryptography have focused on the computational aspect of the ECC hardware, and not on the system integration into a System-on-Chip (SoC) architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performance-limited due to coprocessor data- and instruction-transfers. A dual strategy is proposed to remove the bottleneck: introduction of control hierarchy as well as local storage. The performance of the ECC coprocessor can be almost independent of the selection of bus protocols. Besides performance, the proposed ECC coprocessor is also optimized for scalability. Using design space exploration of a large number of system configurations of different architectures, our proposed ECC coprocessor architecture enables trade-offs between area, speed, and security.