A resource optimized Processor Core for FPGA based SoCs

Authors:
Gerald Hempel;Christian Hochberger
Affiliations:
Dresden University of Technology;Dresden University of Technology
Venue:
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Year:
2007

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Abstract

Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. Typi- cally, the term configurable system on a chip (CSoC) is used for this kind of usage. A key component in such a CSoC is the processor core. Currently, several cores are available for FPGAs. 32 bit processors like MicroBlaze, NIOS 2 or OpenRisc require a lot of resources, whereas very small solutions like PicoBlaze or Lattice Mico8 are not capable of running reasonably complex software. Thus, there is a gap between these two extremes, which we want to fill with our development SpartanMC. This contribution describes its design objectives, architecture, tools, peripherals and compares it to other well known processor cores.