Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Configurable Systems-on-Chip (CSoC)
Proceedings of the 15th symposium on Integrated circuits and systems design
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Reconfigurable Elliptic Curve Cryptosystems on a Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An interactive codesign environment for domain-specific coprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
IEEE Transactions on Computers
A Component-Based Design Environment for ESL Design
IEEE Design & Test
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
Cryptographic Algorithms on Reconfigurable Hardware (Signals and Communication Technology)
A resource optimized Processor Core for FPGA based SoCs
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
Superscalar coprocessor for high-speed curve-based cryptography
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware/software co-design of elliptic curve cryptography on an 8051 microcontroller
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 µP
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integrating several soft processor cores into one FPGA fabric, we can have a hierarchy of controllers in one SoC design. Compared to the previous codesigns trying to optimize the communication overhead between the central control unit and coprocessor over bus by using different bus protocols (e.g. OPB, PLB and FSL) or advanced techniques (e.g. DMA), our approach prevents overhead in bus transactions by introducing a local 8 bit microcontroller, PicoBlaze, in the coprocessor. As a result, the performance of the ECC coprocessor can be almost independent of the selection of bus protocols. To further accelerate the Uni-PicoBlaze based ECC SoC design, a Dual-PicoBlaze based architecture is proposed, which can achieve the maximum instruction rate of 1 instruction/cycle to the ECC datapath. Using design space exploration of a large number of system configurations of different architectures discussed in this paper, our proposed Dual-PicoBlaze based design also shows best trade-off between area and speed.