Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security

  • Authors:
  • Xu Guo;Junfeng Fan;Patrick Schaumont;Ingrid Verbauwhede

  • Affiliations:
  • Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA 24061;ESAT/SCD-COSIC, Katholieke Universiteit Leuven and IBBT, Leuven-Heverlee, Belgium B-3001;Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA 24061;ESAT/SCD-COSIC, Katholieke Universiteit Leuven and IBBT, Leuven-Heverlee, Belgium B-3001

  • Venue:
  • CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
  • Year:
  • 2009

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Abstract

Elliptic Curve Cryptography implementations are known to be vulnerable to various side-channel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of side-channel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security.