A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reconfigurable Elliptic Curve Cryptosystems on a Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Coprocessor for Accelerating Visual Information Processing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration
Journal of VLSI Signal Processing Systems
Implementation of secure applications in self-reconfigurable systems
Microprocessors & Microsystems
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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Systems-on-Chip (SoCs) has become reality now, driven by fast development of CMOS VLSI technologies. Complex system integration onto one single die introduce a set of various challenges and perspectives for industrial and academic institutions. Important issues to be addressed here are cost-effective technologies, efficient and application-tailored hardware/software architectures, and corresponding IP-based EDA methods. Due to exponential increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCs).