Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
An End-to-End Systems Approach to Elliptic Curve Cryptography
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Configurable Systems-on-Chip (CSoC)
Proceedings of the 15th symposium on Integrated circuits and systems design
Hardware architectures for public key cryptography
Integration, the VLSI Journal
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A microcoded elliptic curve processor using FPGA technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed hardware implementations of Elliptic Curve Cryptography: A survey
Journal of Systems Architecture: the EUROMICRO Journal
Designing a Posture Analysis System with Hardware Implementation
Journal of VLSI Signal Processing Systems
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage
Proceedings of the Conference on Design, Automation and Test in Europe
Design of a reconfigurable cryptographic engine
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper presents a System-on-a-Chip (SoC) architecture for Elliptic Curve Cryptosystems (ECC) which targets reconfigurable hardware. A four-level partitioning scheme is described for exploring the area and speed trade-offs. A design generator is used to generate parameterisable building blocks for the configurable SoC architecture. A secure web server, which runs on a reconfigurable soft-processor and an embedded hard-processor, shows over 2000 times speedup when the computationally-intensive operations run on the customised building blocks. The embedded on-chip timer block gives accurate performance information. The design factors of configurable SoC architectures are also discussed and evaluated.