Designing a Posture Analysis System with Hardware Implementation

Authors:
J. G. Coutinho;M. P. Juvonen;J. L. Wang;B. L. Lo;W. Luk;O. Mencer;G. Z. Yang
Affiliations:
Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ;Department of Computing, Imperial College London, London, UK SW7 2EZ
Venue:
Journal of VLSI Signal Processing Systems
Year:
2007

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Abstract

Posture analysis is an active research area in computer vision for applications such as home care and security monitoring. This paper describes the design of a system for posture analysis with hardware acceleration, addressing the following four aspects: (a) a design workflow for posture analysis based on radial shape and projection histogram representations; (b) the implementation of different architectures based on a high-level hardware design approach with support for automating transformations to improve parallelism and resource optimisation; (c) accuracy evaluation of the proposed posture analysis system, and (d) performance evaluation for the derived designs. One of the designs, which targets a Xilinx XC2V6000 FPGA at 90.2 MHz, is able to perform posture analysis at a rate of 1,164 frames per second with a frame size of 320 by 240 pixels. It represents 3.5 times speedup over optimised software running on a 2.4 GHz AMD Athlon 64 3700+ computer. The frame rate is well above that of real-time video, which enables the sharing of the FPGA among multiple video sources.