A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
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Proceedings of the ninth international symposium on Hardware/software codesign
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
NAPA C: Compiling for a Hybrid RISC/FPGA Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems
MASCOTS '97 Proceedings of the 5th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-performance trade-offs for reconfigurable computing
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SOFTENIT: a methodology for boosting the software content of system-on-chip designs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Performance improvements from partitioning applications to FPGA hardware in embedded SoCs
The Journal of Supercomputing
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors & Microsystems
Designing a Posture Analysis System with Hardware Implementation
Journal of VLSI Signal Processing Systems
Low-power warp processor for power efficient high-performance embedded systems
Proceedings of the conference on Design, automation and test in Europe
Two-level microprocessor-accelerator partitioning
Proceedings of the conference on Design, automation and test in Europe
Clock-frequency assignment for multiple clock domain systems-on-a-chip
Proceedings of the conference on Design, automation and test in Europe
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ICCOMP'05 Proceedings of the 9th WSEAS International Conference on Computers
Proceedings of the 13th international symposium on Low power electronics and design
Software optimization for MPSoC: a mpeg-2 decoder case study
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Scalability and parallel execution of warp processing: dynamic hardware/software partitioning
International Journal of Parallel Programming
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-level reconfiguration in the DANAH assistive system
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
Concept-based partitioning for large multidomain multifunctional embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Efficient hardware-based nonintrusive dynamic application profiling
ACM Transactions on Embedded Computing Systems (TECS)
System-level power-performance tradeoffs for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning signal processing applications to different granularity reconfigurable logic
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Speedups from executing critical software segments to coarse-grain reconfigurable logic
ICCOMP'06 Proceedings of the 10th WSEAS international conference on Computers
The Journal of Supercomputing
Performance optimization of embedded applications in a hybrid reconfigurable platform
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
ACM Transactions on Embedded Computing Systems (TECS)
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We present results of extensive hardware/software partitioning experiments on numerous benchmarks. We describe our loop-oriented partitioning methodology for moving critical code from hardware to software. Our benchmarks included programs from PowerStone, MediaBench, and NetBench. Our experiments included estimated results for partitioning using an 8051 8-bit microcontroller or a 32-bit MIPS microprocessor for the software, and using on-chip configurable logic or custom application-specific integrated circuit hardware for the hardware. Additional experiments involved actual measurements taken from several physical implementations of hardware/software partitionings on real single-chip microprocessor/configurable-logic devices. We also estimated results assuming voltage scalable processors. We provide performance, energy, and size data for all of the experiments. We found that the benchmarks spent an average of 80% of their execution time in only 3% of their code, amounting to only about 200 bytes of critical code. For various experiments, we found that moving critical code to hardware resulted in average speedups of 3 to 5 and average energy savings of 35% to 70%, with average hardware requirements of only 5000 to 10,000 gates. To our knowledge, these experiments represent the most comprehensive hardware/software partitioning study published to date.