MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Mapping a Single Assignment Programming Language to Reconfigurable Systems
The Journal of Supercomputing
NetBench: a benchmarking suite for network processors
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Proceedings of the 40th annual Design Automation Conference
Frequent loop detection using efficient non-intrusive on-chip hardware
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
A compiled accelerator for biological cell signaling simulations
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling
Proceedings of the conference on Design, automation and test in Europe - Volume 3
ACM Transactions on Embedded Computing Systems (TECS)
Dynamic FPGA routing for just-in-time FPGA compilation
Proceedings of the 41st annual Design Automation Conference
Optimized Generation of Data-Path from C Codes for FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Hardware/software partitioning of software binaries: a case study of H.264 decode
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
New decompilation techniques for binary-level co-processor generation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 41st annual Design Automation Conference
Dynamic voltage and frequency management based on variable update intervals for frequency setting
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Low-power warp processor for power efficient high-performance embedded systems
Proceedings of the conference on Design, automation and test in Europe
Non-intrusive dynamic application profiler for detailed loop execution characterization
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Embedded Computing Systems (TECS)
An overseer control methodology for data adaptable embedded systems
Proceedings of the 6th International Workshop on Multi-Paradigm Modeling
Energy-aware design of secure multi-mode real-time embedded systems with FPGA co-processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
Efficient heuristic and tabu search for hardware/software partitioning
The Journal of Supercomputing
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Warp processing is a recent computing technology capable of autonomously partitioning the critical kernels within an executing software application to hardware circuits implemented within an on-chip FPGA. While previous performance-driven warp processing has been shown to provide significant performance improvements over software only execution, the dynamic performance improvement of warp processors may be lost for certain application domains, such as real-time systems. Alternatively, as power consumption continue to become a dominant design constraint, we present and thoroughly analyze a low-power warp processing methodology that leverages voltage and/or frequency scaling to substantially reduce power consumption without any performance degradation—all without requiring designer effort beyond the initial software development.