MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A low power unified cache architecture providing power and performance flexibility (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic Reconfiguration in Mobile Systems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An execution environment for reconfigurable computing (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Scheduling Intervals for Reconfigurable Computing
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
Non-intrusive dynamic application profiling for multitasked applications
Proceedings of the 46th Annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 International Conference on Computer-Aided Design
Automatically mapping applications to a self-reconfiguring platform
Proceedings of the Conference on Design, Automation and Test in Europe
XEEMU: an improved xscale power simulator
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Significant research has demonstrated the performance and power benefits of runtime dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are needed to evaluate the performance and power consumption impact of the hardware coprocessor selection. In this paper, we present a profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems. We evaluate the accuracy and fidelity of our online estimation framework for dynamic hardware kernel selection to maximize performance or minimize system power consumption.