Communicating sequential processes
Communicating sequential processes
Executing a Program on the MIT Tagged-Token Dataflow Architecture
IEEE Transactions on Computers
Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder
Proceedings of the 6th international workshop on Hardware/software codesign
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Language and compiler design for streaming applications
International Journal of Parallel Programming - Special issue: The next generation software program
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling of Data Adaptable Reconfigurable Embedded Systems
ECBS '11 Proceedings of the 2011 18th IEEE International Conference and Workshops on Engineering of Computer-Based Systems
Hardware/Software Communication Middleware for Data Adaptable Embedded Systems
ECBS '11 Proceedings of the 2011 18th IEEE International Conference and Workshops on Engineering of Computer-Based Systems
Process algebra: a unifying approach
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
ECBS '12 Proceedings of the 2012 IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems
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The performance of software algorithms can be improved by performing those algorithms on specialized embedded hardware. However, complex algorithms that rely on input data at runtime for configuration have a combinatorial explosion of possible configurations, which has historically put hardware acceleration out of reach for applications wishing to serve large configuration spaces. Data adaptable embedded systems overcome this limitation by allowing for hardware reconfiguration during runtime, but the complexity of the specification of these systems is difficult to manage with traditional techniques. In this paper, a modeling approach is discussed in order to concurrently model two aspects of the final system: dependencies between algorithm tasks, and desired hardware configurations for each task. The contribution of the work is the model-based generation of hardware and software tasks, as well as a control scheme customized to each model that oversees the dynamic reconfiguration process.