A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
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Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
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CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
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Profiling tools for hardware/software partitioning of embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
A Run-Time Reconfigurable Engine for Image Interpolation
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ACM Transactions on Embedded Computing Systems (TECS)
Mapping wireless communication algorithms onto a reconfigurable architecture
The Journal of Supercomputing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
Microprocessors & Microsystems
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In this paper, we present a software framework that implements a formalized methodology for partitioning Digital Signal Processing applications between reconfigurable hardware blocks of different granularity. A hybrid generic reconfigurable architecture is considered, so that the methodology is applicable to a large variety of hybrid reconfigurable systems. The developed framework is composed of analysis, partitioning, and mapping tools. Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware. In this work, the methodology is validated using five real-world digital signal processing applications; an orthogonal frequency division multiplexing transmitter, a cavity detector, a video compression technique, a JPEG encoder, and a wavelet-based image compressor. The experiments report that an average clock cycles decrease of 60.7%, relative to an all fine-grain mapping solution, is achieved using the developed framework for the considered applications.