DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Building and Using a Highly Parallel Programmable Logic Array
Computer - Special issue on experimental research in computer architecture
Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Scheduling using behavioral templates
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A comparison of full and partial predicated execution support for ILP processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
DPGA utilization and application
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Exploiting regularity for low-power design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
String matching on multicontext FPGAs using self-reconfiguration
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
System Design with SystemC
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Instruction generation for hybrid reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A super-scheduler for embedded reconfigurable systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The Garp Architecture and C Compiler
Computer
Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
High-Level Synthesis of Nonprogrammable Hardware Accelerators
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Totem: Custom Reconfigurable Array Generation
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Performance optimization using template mapping for datapath-intensive high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical finite state machines with multiple concurrency models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using configurable computing to accelerate Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Instruction set extension with shadow registers for configurable processors
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
A dictionary construction technique for code compression systems with echo instructions
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Satisfying real-time constraints with custom instructions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Architecture and compilation for data bandwidth improvement in configurable embedded processors
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Proceedings of the 43rd annual Design Automation Conference
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Automatic selection of application-specific instruction-set extensions
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Scalable subgraph mapping for acyclic computation accelerators
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Code transformation strategies for extensible embedded processors
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors & Microsystems
Architecture and compiler optimizations for data bandwidth improvement in configurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rethinking custom ISE identification: a new processor-agnostic method
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Fast, quasi-optimal, and pipelined instruction-set extensions
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
An architecture framework for an adaptive extensible processor
The Journal of Supercomputing
Automatic selection of application-specific reconfigurable processor extensions
Proceedings of the conference on Design, automation and test in Europe
The Instruction-Set Extension Problem: A Survey
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Proceedings of the ICST 2nd international conference on Body area networks
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Recurrence-aware instruction set selection for extensible embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Integration, the VLSI Journal
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
BURS-based instruction set selection
PSI'06 Proceedings of the 6th international Andrei Ershov memorial conference on Perspectives of systems informatics
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Fast, nearly optimal ISE identification with I/O serialization through maximal clique enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving FPGA performance for carry-save arithmetic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Algorithms for the automatic extension of an instruction-set
Proceedings of the Conference on Design, Automation and Test in Europe
The Instruction-Set Extension Problem: A Survey
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Scientific Application Demands on a Reconfigurable Functional Unit Interface
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An efficient algorithm for custom instruction enumeration
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Partitioning signal processing applications to different granularity reconfigurable logic
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-path
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Practical and effective domain-specific function unit design for CGRA
ICCSA'11 Proceedings of the 2011 international conference on Computational science and Its applications - Volume Part V
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
A fast instruction set evaluation method for ASIP designs
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Accelerating loops for coarse grained reconfigurable architectures using instruction extensions
Proceedings of the 2011 ACM Symposium on Research in Applied Computation
Morphable structures for reconfigurable instruction set processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
The Journal of Supercomputing
Exact custom instruction enumeration for extensible processors
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy efficient special instruction support in an embedded processor with compact isa
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Performance optimization of embedded applications in a hybrid reconfigurable platform
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Rapid evaluation of custom instruction selection approaches with FPGA estimation
ACM Transactions on Embedded Computing Systems (TECS)
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Future computing systems need to balance flexibility, specialization, and performance in order to meet market demands and the computing power required by new applications. Instruction generation is a vital component for determining these trade-offs. In this work, we present theory and an algorithm for instruction generation. The algorithm profiles a dataflow graph and iteratively contracts edges to create the templates. We discuss how to target the algorithm toward the novel problem of instruction generation for hybrid reconfigurable systems. In particular, we target the Strategically Programmable System, which embeds complex computational units such as ALUs, IP blocks, and so on into a configurable fabric. We argue that an essential compilation step for these systems is instruction generation, as it is needed to specify the functionality of the embedded computational units. In addition, instruction generation can be used to create soft reconfigurable macros---tightly sequenced prespecified operations placed in the reconfigurable fabric.