A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design strategies for optimal hybrid final adders in a parallel multiplier
Journal of VLSI Signal Processing Systems - Special issue on VLSI arithmetic and implementations
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Optimal Circuits for Parallel Multipliers
IEEE Transactions on Computers
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
High-performance carry chains for FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A faster distributed arithmetic architecture for FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Layout-aware synthesis of arithmetic circuits
Proceedings of the 39th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Multiplier for Virtex FPGA Family
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partial Product Reduction Based on Look-Up Tables
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Automatic synthesis of compressor trees: reevaluating large counters
Proceedings of the conference on Design, automation and test in Europe
Enhancing FPGA performance for arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
A Compact High-Speed Parallel Multiplication Scheme
IEEE Transactions on Computers
IEEE Transactions on Computers
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Efficient synthesis of compressor trees on FPGAs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Improving synthesis of compressor trees on FPGAs via integer linear programming
Proceedings of the conference on Design, automation and test in Europe
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
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To improve FPGA performance for arithmetic circuits that are dominated by multi-input addition operations, an FPGA logic block is proposed that can be configured as a 6:2 or 7:2 compressor. Compressors have been used successfully in the past to realize parallel multipliers in VLSI technology; however, the peculiar structure of FPGA logic blocks, coupled with the high cost of the routing network relative to ASIC technology, renders compressors ineffective when mapped onto the general logic of an FPGA. On the other hand, current FPGA logic cells have already been enhanced with carry chains to improve arithmetic functionality, for example, to realize fast ternary carry-propagate addition. The contribution of this article is a new FPGA logic cell that is specialized to help realize efficient compressor trees on FPGAs. The new FPGA logic cell has two variants that can respectively be configured as a 6:2 or a 7:2 compressor using additional carry chains that, coupled with lookup tables, provide the necessary functionality. Experiments show that the use of these modified logic cells significantly reduces the delay of compressor trees synthesized on FPGAs compared to state-of-the-art synthesis techniques, with a moderate increase in area and power consumption.