IEEE Transactions on Computers
IEEE Transactions on Computers
Adder With Distributed Control
IEEE Transactions on Computers
Counting Responders in an Associative Memory
IEEE Transactions on Computers
IEEE Transactions on Computers
IEEE Transactions on Computers
Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
IEEE Transactions on Computers
IEEE Transactions on Computers
An Upper Bound for the Synthesis of Generalized Parallel Counters
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
IEEE Transactions on Computers
On Multiple Operand Addition of Signed Binary Numbers
IEEE Transactions on Computers
The Two's Complement Quasi-Serial Multiplier
IEEE Transactions on Computers
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Self-Testing Embedded Borden t-UED Code Checkers for t=2kq-1 with q=2m-1
Journal of Electronic Testing: Theory and Applications
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Computing Naturally in the Billiard Ball Model
UC '09 Proceedings of the 8th International Conference on Unconventional Computation
IEEE Transactions on Circuits and Systems II: Express Briefs
Compressor tree synthesis on commercial high-performance FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Direct compare of information coded with error-correcting codes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in repair analyzer with optimal repair rate for word-oriented memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Multiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called parallel counters. In this paper three separate types of counters are described, analyzed, and compared. The first counter consists of a network of full adders. The second counter uses a combination of full adders and fast adders (that may be realized with READ-ONLY memories), while the third type of counter uses quasi-digital (i.e., analog current summing) techniques to generate an analog signal proportional to the count which is then digitized.