Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
IEEE Transactions on Computers
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer arithmetic: algorithms and hardware designs
Computer arithmetic: algorithms and hardware designs
Introduction to Parallel Processing: Algorithms and Architectures
Introduction to Parallel Processing: Algorithms and Architectures
Accumulative parallel counters
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System
IEEE Transactions on Computers
IEEE Transactions on Computers
Analog Integrated Circuits and Signal Processing
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New counting-based methods for comparing the Hamming weight of a binary vector with a constant, as well as comparing the Hamming weights of two input vectors, are proposed. It is shown. that the proposed comparators are faster and simpler, both in asymptotic sense and for moderate vector lengths, compared with the best available fully digital designs. These speed and cost advantages result from a more efficient population counting, as well as the merger of counting and comparison operations, via accumulative and up/down parallel counters.