On the scheduling of variable latency functional units
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design optimizations for microprocessors at low temperature
Proceedings of the 41st annual Design Automation Conference
Low-power carry-select adder using adaptive supply voltage based on input vector patterns
Proceedings of the 2004 international symposium on Low power electronics and design
Microarchitecture and Design Challenges for Gigascale Integration
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Distributing the Frontend for Temperature Reduction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Variability and energy awareness: a microarchitecture-level perspective
Proceedings of the 42nd annual Design Automation Conference
Variable latency caches for nanoscale processor
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reducing parity generation latency through input value aware circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
IEEE Transactions on Circuits and Systems II: Express Briefs
Power characterisation for fine-grain reconfigurable fabrics
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Proceedings of the 37th annual international symposium on Computer architecture
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate characterization of the variability in power consumption in modern mobile processors
HotPower'12 Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems
Exploiting input variations for energy reduction
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section ESFH'12, ESTIMedia'11 and Regular Papers
Modeling the impact of permanent faults in caches
ACM Transactions on Architecture and Code Optimization (TACO)
A column parity based fault detection mechanism for FIFO buffers
Integration, the VLSI Journal
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Parameter variations, which are increasing along with advances in process technologies, affect both timing and power. Variability must be considered at both the circuit and microarchitectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits. This article presents an overview of the main sources of variability and surveys variation-tolerant circuit and microarchitectural approaches.