ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Leakage and leakage sensitivity computation for combinational circuits
Proceedings of the 2003 international symposium on Low power electronics and design
A critical analysis of application-adaptive multiple clock processors
Proceedings of the 2003 international symposium on Low power electronics and design
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Microarchitecture parameter selection to optimize system performance under process variation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Impact of process variations on multicore performance symmetry
Proceedings of the conference on Design, automation and test in Europe
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Characterizing chip-multiprocessor variability-tolerance
Proceedings of the 45th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Measuring and modeling variabilityusing low-cost FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variability-aware robust design space exploration of chip multiprocessor architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Shapeshifter: Dynamically changing pipeline width and speed to address process variations
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
EVAL: Utilizing processors with variation-induced timing errors
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Tolerating process variations in large, set-associative caches: The buddy cache
ACM Transactions on Architecture and Code Optimization (TACO)
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
Mitigating the impact of variability on chip-multiprocessor power and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing variability in chip-multiprocessors with adaptive body biasing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Energy-efficient scheduling of real-time periodic tasks in multicore systems
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Computer and System Sciences
Exploiting process variability in voltage/frequency control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes microarchitecture-level models for Within Die (WID) process and system parameter variability that can be included in the design of high-performance processors. Since decisions taken at microarchitecture level have the largest impact on both performance and power, on one hand, and global variability effect, on the other hand, models and associated metrics are needed for their joint characterization and analysis. To assess how these variations affect or are affected by microarchitecture decisions, we propose a joint performance, power and variability metric that is able to distinguish among various design choices. As a design-driver for the modeling methodology, we consider a clustered high-performance processor implementation, along with its Globally Asynchronous, Locally Synchronous (GALS) counterpart. Results show that, when comparing the baseline, synchronous and its GALS counterpart, microarchitecture-driven impact of process variability translates into 2-10% faster local clocks for the GALS case, while when taking into account the effect of on-chip temperature variability, local clocks can be 8-18% faster. If, in addition, voltage scaling (DVS) is employed, the GALS architecture with DVS is 26% better in terms of the joint quality metric employing energy, performance, and variability.