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A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
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Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by sub-wavelength lithography, will pose a major challenge for design and reliability of future high performance microprocessors in nanometer technologies. In this paper, we present the impact of these variations on processor functionality, predictability and reliability. We propose design and CAD solutions for variation tolerance. We conclude this paper with soft error rate scaling trends and soft error tolerant circuits for reliability enhancement.