Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Proceedings of the 43rd annual Design Automation Conference
Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications
Proceedings of the 2nd international conference on Nano-Networks
Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage
Proceedings of the 2009 International Conference on Computer-Aided Design
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 47th Design Automation Conference
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
From Transistors to NEMS: Highly Efficient Power-Gating of CMOS Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse
Proceedings of the 49th Annual Design Automation Conference
Lighting the dark silicon by exploiting heterogeneity on future processors
Proceedings of the 50th Annual Design Automation Conference
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Nano-electro-mechanical relays for FPGA routing: experimental demonstration and a design technique
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low power dynamic OR gates, SRAM cells, and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60--80% lower switching power and almost zero leakage power consumption with minor delay penalty. However, the hybrid gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that the proposed hybrid SRAM cell can achieve almost 8X lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in upto three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.