Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications
Proceedings of the 44th annual Design Automation Conference
An Energy-Efficient Processor Architecture for Embedded Systems
IEEE Computer Architecture Letters
Integrated circuit design with NEM relays
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Complementary nano-electromechanical switches for ultra-low power embedded processors
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Efficient FPGAs using nanoelectromechanical relays
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Proceedings of the International Conference on Computer-Aided Design
Energy efficient computation: A silicon perspective
Integration, the VLSI Journal
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Heterogeneity, programmability and parallelism are expected to be the key drivers for future nanoelectronics systems. The proposed work builds on these key drivers to achieve an energy-efficient, adaptive, and reliable computing framework. The primary intellectual merit of this effort lies in the heterogeneous integration of two fundamentally different state variables - charge-based electronics and electromechanical. We exploit the complementary capabilities of the two layers - high-performance operation of nanoscale FET and ultralow-power and harsh environment operation of NEMS - to merge the benefit of both. The layers are used in a symbiotic manner where each addresses the limitations of the other. The leakage/programmability issues in FET layer are addressed by exploiting the near-zero leakage and low ON-resistance of NEMS switches. The reliability and drivability issues of NEMS layer are addressed by FETs. The innovative memory based computing architecture exploits the density advantage of nanoscale memory to reduce the programmable interconnect overhead of traditional reconfigurable computing. It enables realizing custom computing functions in a core-based architecture to improve energy efficiency through hardware acceleration. The fundamental questions on the effectiveness of nanomechanical computing and the physics of its interaction with charge-based nanoelectronics are investigated.