NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Defect and Fault Tolerance of Reconfigurable Molecular Computing
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Design of a QCA Memory with Parallel Read/Serial Write
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Scalable defect mapping and configuration of memory-based nanofabrics
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
Journal of Electronic Testing: Theory and Applications
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Low power FPGA design using hybrid CMOS-NEMS approach
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fault tolerant placement and defect reconfiguration for nano-FPGAs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Prospects for the development of digital CMOL circuits
NANOARCH '07 Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
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Emerging nanoscale devices hold tremendous potential in terms of integration density, low power operation and switching speed. Unlike CMOS devices, however, majority of these devices are not suitable for implementing cascaded, irregular logic structure. On the other hand, dense and periodic structures of most emerging nanodevices as well as their bi-stable nature make them amenable to large high-density memory array design. Moreover, self-assembly of many nanostructures is efficient for a bottom-up system design flow. Hence, reconfigurable computing paradigms that use memory as underlying computing element, appear promising for these devices. In this paper, first we study nanoscale FPGA, which extends conventional spatial CMOS FPGA architecture using nanoscale memory and interconnect. Next, we focus on a time-multiplexed memory based computing paradigm that employs two-dimensional memory for improved performance, integration density and resource usage.