Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Design of a QCA Memory with Parallel Read/Serial Write
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Seven Strategies for Tolerating Highly Defective Fabrication
IEEE Design & Test
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
CAEN-BIST: Testing the NanoFabric
ITC '04 Proceedings of the International Test Conference on International Test Conference
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 45th annual Design Automation Conference
A circuit-software co-design approach for improving EDP in reconfigurable frameworks
Proceedings of the 2009 International Conference on Computer-Aided Design
A variation-aware preferential design approach for memory based reconfigurable computing
Proceedings of the 2009 International Conference on Computer-Aided Design
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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While the emerging nanoscale devices show promises in terms of integration density and computing power, system design with these devices involve some major challenges, such as bottom-up design approach, effective integration with CMOS and defect tolerance. To address some of these challenges, we propose MBARC, a reconfigurable framework using memory as the primary computing element. The proposed framework leverages on the reported advantages of memory array design with nanodevices, which are compatible to fabrication into dense and regular structures. The main idea is to partition a logic circuit, implement the partitions as multi-input multi-output lookup tables in a memory array, and then use a simple CMOS-based scheduler to evaluate the partitions in topological time-multiplexed manner. Compared to existing reconfigurable nanocomputing models, the proposed memory based computing has three major advantages: 1) it minimizes the requirement of programmable interconnects, thus, saving design cost; 2) it minimizes the number of CMOS interfacing elements (required for level restoration and cascading logic blocks); 3) existing techniques for defect tolerance in memory array can be easily extended to this framework. Simulation results for a set of ISCAS benchmarks show average improvement of 32% in area, 21% in delay and 34% in energy per vector compared to nanoscale FPGA implementation.