Design of a QCA Memory with Parallel Read/Serial Write

Authors:
M. Ottavi;V. Vankamamidi;F. Lombardi;S. Pontarelli;A. Salsano
Affiliations:
Northeastern University Boston;Northeastern University Boston;Northeastern University Boston;University of Rome;University of Rome
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

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Abstract

This paper presents a novel memory architecture for implementation by Quantum-dot Cellular Automata (QCA). The proposed architecture combines the advantages of reduced area of a serial memory with the reduced latency in the read operation of a parallel memory. An extensive evaluation with respect to latency and area is pursued. For area analysis, a novel characterization which considers cells in the logic circuitry, interconnect as well as the unused portion of the Cartesian place as QCA layout, is proposed.