A design of and design tools for a novel quantum dot based microprocessor
Proceedings of the 37th Annual Design Automation Conference
Computer
A Memory Design in QCAs using the SQUARES Formalism
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Design of a QCA Memory with Parallel Read/Serial Write
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Modeling QCA Defects at Molecular-level in Combinational Circuits
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Incorporating standard CMOS design Process methodologies into the QCA logic design process
IEEE Transactions on Nanotechnology
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
Testing of quantum cellular automata
IEEE Transactions on Nanotechnology
A line-based parallel memory for QCA implementation
IEEE Transactions on Nanotechnology
Asynchronous Solutions for Nanomagnetic Logic Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Emerging technologies have attracted a substantial interest in overcoming the physical limitations of CMOS as projected at the end of the Technology Roadmap; among these technologies, quantum-dot cellular automata (QCA) relies on different and novel paradigms to implement dense, low power circuits and systems for high-performance computing. As applicable to existing technologies, a hierarchical process can be utilized to facilitate the design of QCA circuits. Tools and methodologies both at system and physical levels are required to support all design phases. This article presents an HDL model to describe QCA “devices” (also referred elsewhere in the technical literature as building blocks, i.e., majority voter, inverter, wire, crossover) and facilitate the evaluation of their design. This tool, referred to as HDLQ, allows a designer to verify the logic characteristics of a QCA system, while supporting within a design environment different operational mechanisms (such as fault injection) and the unique features of QCA (such as bidirectionality and timing/clocking partitioning). The applicability of this design environment to various memory circuits for logic and timing verification is presented in detail. Various defective conditions for kinks due to thermodynamic effects and permanent faults due to manufacturing defects are considered for injection.