Tile-based design of a serial memory in QCA
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design of a QCA Memory with Parallel Read/Serial Write
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Tile-based QCA design using majority-like logic primitives
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HDLQ: A HDL environment for QCA design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire
Journal of Electronic Testing: Theory and Applications
A shift-register-based QCA memory architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A test generation framework for quantum cellular automata circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Improving line-based QCA memory cell design through dual phase clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Layout design of manufacturable quantum-dot cellular automata
Microelectronics Journal
A comparative analysis and design of quantum-dot cellular automata memory cell architecture
International Journal of Circuit Theory and Applications
New robust QCA D flip flop and memory structures
Microelectronics Journal
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We present a formalism for implementing circuits with Quantum-dot Cellular Automata (QCA), comprising a set of standard circuit elements with uniform layout rules. The formalism simplifies circuit design from an engineering perspective and overcomes an observed sensitivity of QCA systems to input delays. A design for an addressable shift register is implemented, and promises considerable density gains over conventional CMOS.