A Memory Design in QCAs using the SQUARES Formalism
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Towards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Quantum-Dot Cellular Automata Design Guideline
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Serial Memory by Quantum-Dot Cellular Automata (QCA)
IEEE Transactions on Computers
Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study
Journal of Systems Architecture: the EUROMICRO Journal
Adder and Multiplier Design in Quantum-Dot Cellular Automata
IEEE Transactions on Computers
A new quantum-dot cellular automata full-adder
Microelectronics Journal
Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata
Microelectronics Journal
Improving line-based QCA memory cell design through dual phase clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
A line-based parallel memory for QCA implementation
IEEE Transactions on Nanotechnology
The Robust QCA Adder Designs Using Composable QCA Building Blocks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA
IEEE Transactions on Nanotechnology
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Quantum dot Cellular Automata (QCA) is one of the candidate technologies to be replaced with CMOS. Using this technology, extra low power, extremely dense and very high speed structure is achieved. Since flip flops and memory cells are fundamental building blocks of digital circuits, constructing an efficient, dense, and simple QCA memory structure is of great importance. In this paper, using a robust 2:1 multiplexer, efficient level triggered and edge triggered QCA D flip flops and a memory cell with set/reset ability will be introduced. Simulation results demonstrate that the proposed desgins have efficient structures in terms of area, delay and complexity. Also, it is worth mentioning that these designs in contrast to the previous structures do not need any crossover wire. QCA designer, a common QCA layout design and a verification tool is employed to verify and simulate the proposed circuits.