Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A Memory Design in QCAs using the SQUARES Formalism
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Design of a QCA Memory with Parallel Read/Serial Write
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
QCADesigner: a rapid design and Simulation tool for quantum-dot cellular automata
IEEE Transactions on Nanotechnology
A line-based parallel memory for QCA implementation
IEEE Transactions on Nanotechnology
Novel RAM cell designs based on inherent capabilities of quantum-dot cellular automata
Microelectronics Journal
p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata
ACM Journal on Emerging Technologies in Computing Systems (JETC)
New robust QCA D flip flop and memory structures
Microelectronics Journal
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This paper describes a line-based, quantum-dot cellular automata (QCA) memory cell design that is synchronized by a dual-phase clocking scheme. In line-based QCA memory cells, data bits are stored oscillating along QCA lines. The best known line-based memory cell implementation requires three new clocking zones in addition to the four clocking zones defined by the conventional QCA clocking scheme and utilizes three parallel clocking zones per cell. The proposed memory cell requires only two new clocking zones and utilizes two parallel clock zones per memory cell; permitting less CMOS circuity for clock design and denser QCA system implementations. Furthermore, read throughput is improved to one operation per clock cycle (from one read per two clock cycles). Simulations with the QCADesigner simulator are performed to verify the functionality of the proposed QCA memory cell.